The present invention relates generally to a method of manufacturing semiconductor memory devices and more particularly, to a method of manufacturing flash memory devices.
In general, a memory cell pattern of a flash memory device has a structure in which a semiconductor substrate 11, a tunnel oxide film 13, a floating gate 14, an ONO dielectric film 15 and a control gate 16 are sequentially laminated, as shown in FIG. 1. Recently, the tunnel oxide film 13 is not formed of only a pure silicon oxide film (SiO2), but is formed to include an oxynitride layer in which nitrogen is incorporated into silicon oxide (SiO2). To form the tunnel oxide film of oxynitride, a process of depositing the silicon oxide film (SiO2) and a process of combining nitrogen and the silicon oxide film (SiO2) are sequentially performed on the semiconductor substrate 11. Charge breakdown (Qbd), Fowler-Nordheim (F-N) stress, hot carrier injection and endurance characteristics of the tunnel oxide film formed of oxynitride are superior to those of a tunnel oxide film comprised of pure silicon oxide film (SiO2).
It has been discovered that lower concentrations of nitrogen in the tunnel oxide film, tend to trap more charge at the floating gate, i.e., the threshold voltage of the memory cell is shifted. Therefore, the concentration of nitrogen in the tunnel oxide film needs to be maintained within a predetermined range. As the demand for more highly integrated semiconductor memories leads to smaller features and higher device densities on a chip, the thickness of the tunnel oxide film is reduced. As the thickness of the tunnel oxide film is reduced, the quantity of nitrogen to be incorporated into the tunnel silicon oxide film (SiO2) film should be correspondingly reduced. The above issue becomes an even bigger concern when a flash memory device has an ultra fine pattern with typical dimensions of 70 nm or less. Additional issues arise at these feature dimensions because the breakdown characteristics of the tunnel oxide film are degraded by electrons that move through the tunnel oxide film, and the gate characteristics are degraded as programming and erasing operations are repeatedly performed on memory cells.
The ONO dielectric film 15 has a structure in which an ONO2 oxide film 15a, an ONO2 nitride film 15b and an ONO3 oxide film 15c are sequentially layered. The ONO dielectric film 15 has a significant influence on the electrical characteristics for the program, erase and read operations of the memory cells. The thickness of the ONO dielectric film 15, as well as the quality of each of the three layers, ONO2 oxide 15a, ONO2 nitride 15b and ONO3 oxide film 15c all have a significant influence on the operating characteristics of the memory cells. Of these, the thickness and quality of the ONO2 oxide film 15a have the greatest effect on the charge leakage and charge retention characteristics of a cell transistor. This is because the function of the ONO2 oxide film 15a is to block leakage current from electrons injected into the floating gate 14. Therefore, the ONO2 oxide film 15a should be formed to thin, yet of high quality.
The ONO2 oxide film 15a and the ONO3 oxide film 15c are generally deposited by a Chemical Vapor Deposition (CVD) method using DSC (Dichlorosilane, SiH2Cl2) or silane (SiH4). The quality of an oxide film formed by CVD is, however, inferior to that of oxide films formed by a thermal dry and wet oxidization process. Therefore, to form an oxide film with a thin thickness and a good film quality, a thermal oxidization process is generally used. However it is difficult to form a thin ONO2 oxide film 15a on the floating gate 14 by means of the thermal oxidization process because the floating gate 14 is a doped polysilicon film.
Since the polysilicon film constituting the floating gate 14 has a grain structure, there are grooves at the grain boundaries on its surface, as shown in FIG. 1. When the ONO2 oxide film 15a is deposited on the floating gate 14, the ONO2 oxide film 15a becomes thicker in the neighborhood of the grain boundary grooves on the surface of the polysilicon film owing to thermodynamic driving forces. Not only does the ONO2 oxide film 15a have increased thickness, but it also has an unstable interface.
In addition, the as deposited ONO2 nitride film 15b often has a porous structure and is brittle. To improve the quality of the ONO2 nitride film 15b, a high-temperature anneal process is performed after depositing the ONO2 nitride film 15b. For this reason, to attain the required operating characteristics (charge leakage and charge retention) necessary for memory cells, a high-temperature wet anneal process for improving the film quality of the ONO dielectric film 15 is carried out for a long time under atmospheric pressure following deposition of the ONO dielectric film 15.
However, when the ONO dielectric film 15 is exposed under a high-temperature wet atmosphere for a long time, a thermally driven regrowth within ONO dielectric film 15 leads to a “punch” phenomenon in the ONO2 nitride film layer 15b. This results in changing the dielectric constant of the ONO dielectric film 15, and the read, program, and erase operational characteristics of a cell transistor are degraded.